RAM 6.0 BUX II Series Guia do Utilizador descarregar pdf (Página 23)

7. Devices

Ethernet Controllers

VxWorks is very “network oriented,” at least during the development phase; thus,

it is highly desirable to have a networking interface available. The interface can be

used for booting and downloading application code as well as application-specific

inter-processor communication. VxWorks provides a device-independent

interface to Ethernet controllers through netLib, which permits the use of RPC and

NFS and other Internet protocols.

There are two basic classes of Ethernet devices on the market: those that share

memory with the CPU and other bus devices, and those that maintain a private

packet buffer hidden from the CPU.

The devices that share memory with the CPU do so through DMA bus cycles. This

implies that the device is sharing cycles on the bus while it is transmitting and

receiving data. This can have a non-deterministic effect on the application.

The devices that hide the packet buffer from the CPU typically require CPU

processing to move the packet data in and out of the private buffer. This is

commonly done with byte or word moves to or from a register on the device. This

model may provide better deterministic behavior because the CPU is in complete

control of the movement of packet data. However, if the CPU is responsible for

transferring data, the typical result is lower network throughput and increased

processor load. The system designer needs to determine the trade-off between

higher performance and more deterministic system behavior.

Within the shared memory class of devices is another classification: those devices

that only deal with contiguous memory, and those devices that deal with

fragmented memory. Devices that can deal with fragmented memory are generally

preferred for VxWorks, because the network interface driver exchanges mbufs

with the protocol modules, and mbufs are basically memory fragments. If a device

can only deal with contiguous memory, the driver must copy the packet data

between mbufs and this contiguous memory, which can affect performance.

If a device from the shared memory class is used, it is advantageous to select one

that does not have any addressing or memory segment restrictions. This keeps the

driver simpler, more efficient, and more generic.

If data caching is an issue with the selected processor, it is advantageous if the

Ethernet controller/DMA device and the CPU have hardware cache coherency

support such as the snoop lines on the MC68040 and the Intel 82596, or if the

Ethernet device and the memory it uses can be “marked” as non-cacheable. If

hardware support is not available, the driver must take into consideration cache

coherency, performing cache-invalidate or cache-flush operations at appropriate

times. This makes the driver more complex and less generic.

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