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3 Porting a BSP to Custom Hardware

3.3 Finalizing Your BSP

3.3.5 Cache, MMU, and DMA Devices

The next step in the BSP development process is to get the BSP working with cache

and MMU enabled.

The standard cache and MMU libraries are enabled and initialized by the usrInit( )

code in usrConfig.c. The call to cacheLibInit( ) is marked by #ifdef

INCLUDE_CACHE_SUPPORT. To enable cache, define

INCLUDE_CACHE_SUPPORT, and define USER_I_CACHE_MODE and

USER_D_CACHE_MODE to CACHE_ENABLED in config.h. You may also need to

adjust any conditional compilation you are using for BSP debugging.

Similarly, the MMU is enabled with a call to usrMmuInit( ) in the usrInit( ) routine

located in usrConfig.c. The call to usrMmuInit( ) is surrounded by #ifdef

INCLUDED_MMU_BASIC or INCLUDE_MMU_FULL.

Enabling the cache or MMU is often a source of problems in the BSP development

process. Although the system may work properly with cache and MMU disabled,

it is often the case that the system fails to operate correctly when cache or MMU is

first enabled. Typically, the cause of the failure is missing or incorrect code in the

BSP and is not usually related to something wrong in the cache library. For

example, with cache disabled, an Ethernet device’s descriptor table is never

exposed to cache coherency problems. However, once cache is enabled, a problem

manifests itself. Depending on the nature of the missing or incorrect code, network

traffic may stop or the entire system may crash.

For more information on enabling the cache and MMU, see the VxWorks Hardware

Considerations Guide: Virtual Memory Library and VxWorks Device Driver Developer’s

Guide: Cache Considerations. Also, see A.3 Cache and MMU, p.133, for more

information on troubleshooting problems that are encountered when enabling

cache and MMU for the first time.

The following sections describe optional customizations related to cache support

for your BSP.

sysCache.c, sysCacheLockLib.c, and Other Custom Cache Support

For boards that use an L2 cache not included in the processor chip, neither the

architecture nor the CPU code can include support for this cache. In this

configuration, cache is treated, in some ways, as an external device with a custom

interface to the BSP and application programs. Normally, this interface is kept in

the sysCache.c file.

In general, this cache support library depends heavily on the board design.

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RAM 6.0 BUX II Series Guia do Utilizador Página 83