RAM 7.0 Guia do Utilizador descarregar pdf (Página 103)

DS512 March 1, 2011 www.xilinx.com 103

Product Specification

LogiCORE IP Block Memory Generator v6.1

Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA: Memory with Core Output Reg-

isters

When only Register Port [A|B] Output of Memory Core is selected, the Kintex-7/Virtex-6/Virtex-

6/Virtex-5/Virtex-4 device’s embedded registers are disabled for the selected ports in the generated

core, as shown in Figure 70.

Port A or Port B

 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives

 Register Port A Output of Memory Core  Register Port B Output of Memory Core

X-Ref Target - Figure 70

Figure 70: Kintex-7, VIrtex-7, Virtex-6, Virtex-5, or Virtex-4 Block Memory Generated with

Block Memory Generator Core

Core

Output

Registers

Latches

FALSE

Block RAM Primitives

Block RAM

Embedded

Output Registers

N/A

Latches

SSR*

Block RAM

Embedded

Output Registers

N/A

Latches

SSR*

Block RAM

Embedded

Output Registers

N/A

Latches

Use REGCE Pin

REGCE

MUX

CLK

RST

DOUT

R* : The reset (R) of the flop is gated by CE

TRUE

1 2 ... 98 99 100 101 102 103 104 105 106 107 108 ... 117 118

Comentários a estes Manuais

Sem comentários

RAM 7.0 Guia do Utilizador Página 103

Comentários a estes Manuais

Manuais e produtos relacionados com Amplificadores áudio RAM 7.0