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Product Specification

LogiCORE IP Block Memory Generator v6.1

When using data-width aspect ratios, the primitive type dimensions are chosen with respect to the A

port Write width. Note that primitive selection may limit port aspect ratios as described in Aspect Ratio

Limitations, page 29. When using the byte Write feature in Kintex-7, Virtex-7, Virtex-6, Virtex-5, Virtex-

4, Spartan-6, and Spartan-3A/3A DSP devices, only the 2kx9, 1kx18, and 512kx36 primitive choices are

available.

Selectable Width and Depth

The Block Memory Generator generates memories with widths from 1 to 1152 bits, and with depths of

two or more words. The memory is built by concatenating block RAM primitives, and total memory

size is limited only by the number of block RAMs on the target device.

Write operations to out-of-range addresses are guaranteed not to corrupt data in the memory, while

Read operations to out-of-range addresses will return invalid data. Note that the set/reset function

should not be asserted while accessing an out-of-range address as this also results in invalid data on the

output in the present or following clock cycles depending upon the output register stages of the core.

Operating Mode

The operating mode for each port determines the relationship between the Write and Read interfaces

for that port. Port A and port B can be configured independently with any one of three Write modes:

Write First Mode, Read First Mode, or No Change Mode. These operating modes are described in the

sections that follow.

Virtex-6 FPGA 256x72 512x72 (SP RAM/ROM and SDP configurations only)

(2)

Virtex-5 FPGA 16kx1 64kx1, 32kx1, 16kx1

Virtex-5 FPGA 8kx2 16kx2, 8kx2

Virtex-5 FPGA 4kx4 8kx4, 4kx4

Virtex-5 FPGA 2kx9 4kx9, 2kx9

Virtex-5 FPGA 1kx18 2kx18, 1kx18

Virtex-5 FPGA 512x36 1kx36

Virtex-5 FPGA 256x72

512x72 (Single and Simple Dual-port RAMs and Single Port

ROMs only)

Virtex-4 FPGA 16kx1 32kx1, 16kx1

Virtex-4 FPGA 8kx2 8kx2

Virtex-4 FPGA 4kx4 4kx4

Virtex-4 FPGA 2kx9 2kx9

Virtex-4 FPGA 1kx18 1kx18

Virtex-4 FPGA 512x36 512x36

Virtex-4 FPGA 256x72 256x72 (Single Port configurations only)

Notes:

1. Spartan-3 FPGAs and its derivatives, including Spartan-3E and Spartan-3A/3A DSP devices.

2. Refer to Additional memory collision restrictions in Collision Behavior, page 30.

Table 6: Memory Primitives Used Based on Architecture (Supported in Native BMG) (Cont’d)

Architecture

Primitive

Selection

Primitives

Used

1 2 ... 20 21 22 23 24 25 26 27 28 29 30 ... 117 118

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