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LogiCORE IP Block Memory Generator v6.1

16 www.xilinx.com DS512 March 1, 2011

Product Specification

Figure 16 illustrates an example of AXI “narrow” Read bursting with a 32-bit block RAM and the AXI

master request is a half-word burst of 4 data beats. ARSIZE is set to 001b.

For more details on AXI4 Narrow Transactions refer to the “Narrow transfers” section of the AXI

protocol specification [Ref 1].

AXI4 Unaligned Transactions

Unaligned burst transfers for example, occur when a 32-bit word burst size does not start on an address

boundary that matches a word memory location. The starting memory address is permitted to be

X-Ref Target - Figure 16

Figure 16: AXI4 Narrow Read Burst Transactions

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