RAM 7.0 Guia do Utilizador descarregar pdf (Página 41)

DS512 March 1, 2011 www.xilinx.com 41

Product Specification

LogiCORE IP Block Memory Generator v6.1

does not appear at the output. At the time of the third reset, only REGCEA is high; so the reset value is

asserted at the output for only one clock cycle.

Asynchronous Reset

The Spartan-6 device architecture provides the ability to asynchronously reset the memory latch and

embedded output register. The Block Memory Generator core extends this capability to the core output

registers and the primitive output registers constructed out of fabric. The GUI provides the option to

choose between the two reset types: synchronous and asynchronous. When using an asynchronous

reset, the reset value is asserted immediately when the reset input goes high, but is deasserted only at

the following clock edge when reset is low and enable is high. Figure 45 illustrates an asynchronous

reset operation in Spartan-6 devices.

Controlling Reset Operations in Kintex-7, Virtex-7, Virtex-6, and Spartan-6 FPGAs

The reset operation in Kintex-7, Virtex-7, Virtex-6, and Spartan-6 devices is dependent on the following

generics:

• Use RST[A

|B] Pin: These options determine the presence or absence of RST pins at the output of

the core.

• Reset Memory Latch (for Port A and Port B): This option determines if the memory latch will be

reset in addition to the embedded primitive output register for the respective port.

• Reset Priority (for Port A and Port B): This option determines the priority of clock enable over

reset or reset over clock enable for the respective port.

X-Ref Target - Figure 44

Figure 44: Reset Gated by CE in Kintex-7, Virtex-7, Virtex-6, and Spartan-6 Devices with

Reset Memory Latch Option

X-Ref Target - Figure 45

Figure 45: Asynchronous Reset

DOUTA[15:0]

CLKA

ADDRA

0000

aa cc dd

RSTA

INIT_VAL MEM(bb)

OPERATION

RESET READREAD READREAD

ENA

REGCEA

RESET

MEM(dd)

READ

INIT_VAL

RESET

CLKA

aa bb cc dd ee

0000

MEM(aa)

INIT_VAL

ENA

RSTA

ADDRA

DOUTA[15:0]

Operation

ReadReset Read Reset

MEM(cc) MEM(dd)

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 117 118

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