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LogiCORE IP Block Memory Generator v6.1

46 www.xilinx.com DS512 March 1, 2011

Product Specification

Figure 47 shows the assertion of the SBITERR and DBITERR output signals when errors are injected

through the error injection pins during a Write operation.

When the INJECTSBITERR and INJECTDBITERR inputs are asserted together at the same time for the

same address during a Write operation (as in the case of address 3 in Figure 47), the INJECTDBITERR

input takes precedence, and only the DBITERR output is asserted for that address during a Read

operation. The data output for this address is not corrected.

Soft Error Correction Capability and Error injection

This section describes the implementation and usage of the Soft Error Correction Control (Soft ECC)

module that is supported in the Block Memory Generator.

Overview

The Soft ECC module detects and corrects all single-bit errors in a code word consisting of up to 64 bits

of data and up to eight parity bits. In addition, it detects double-bit errors in the data. This design uses

Hamming code, which is an efficient method for ECC operations.

Features

• Supports Soft ECC for data widths less than or equal to 64 bits in Kintex-7, Virtex-7, Virtex-6 and

Spartan-6 devices

• Uses Hamming error code correction

X-Ref Target - Figure 47

Figure 47: Assertion of SBITERR and DBITERR Signals by Using Error Injection Pins

CLK

OPERATION

WRITE

READ

ADDR

0 2 3 1 2 3 4

INJECTSBITERR

INJECTDBITERR

DIN

0 B C D E F 9

DOUT

0 A B C A Bx Cx

SBITERR

DBITERR

WRITE WRITE

READ READ READ

SBITERR

Corrected

Data

DBITERR

Incorrect

Data

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 117 118

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