RAM 7.0 Guia do Utilizador descarregar pdf (Página 94)

LogiCORE IP Block Memory Generator v6.1

94 www.xilinx.com DS512 March 1, 2011

Product Specification

44 C_HAS_REGCEB Integer 0

Determines whether port B has an

enable pin for its output register.

45 C_HAS_RSTB Integer 0

Determines whether port B has

reset pin.

46 C_INITB_VAL String “…”

Defines initialization/power-on value

for port B output.

47 C_USE_BYTE_WEB Integer 0, 1

Determines whether byte-Write

feature is used on port B. This value

is the same as

C_USE_BYTE_WEA, since there is

only a single byte Write enable

provided.

48 C_WEB_WIDTH Integer 1 to 128 Defines width of WEB pin for port B.

49 C_USE_ECC Integer 0

For Kintex-7, Virtex-7, and Virtex-6,

determines ECC options:

•0 = No ECC

•1 = ECC

50 C_RST_TYPE String

([“SYNC”, “ASYNC”] :

“SYNC”)

Type of Reset: synchronous or

asynchronous. This parameter

applies only for Spartan-6 devices.

51 C_RST_PRIORITY_A String ([“CE”, “SR”] : “CE”)

In the absence of output registers,

this selects the priority between the

RAM ENA and the RSTA pin. When

using output registers, this selects

the priority between REGCEA and

the RSTA pin.

52 C_RSTRAM_A Integer 0

Applicable for Kintex-7, Virtex-7,

Virtex-6 and Spartan-6 devices. If

the value of this generic is 1, both

the memory latch and the

embedded primitive output register

of Port A are reset. If this value is 0,

then for Spartan-3A DSP and

Spartan-6 devices, the primitive

output register is built out of fabric,

and only the output register is reset

(the memory latch is not reset). If

this value is 0 for Kintex-7, Virtex-7,

and Virtex-6 devices, then only the

embedded output register of the

primitive is reset (the memory latch

is not reset).

Setting this option to 1 results in the

output reset value being asserted for

two clock cycles.

53 C_RST_PRIORITY_B String ([“CE”, “SR”] : “CE”)

In the absence of output registers,

this selects the priority between the

RAM ENB and the RSTB pin. When

using output registers, this selects

the priority between REGCEB and

the RSTB pin.

Table 44: AXI4 Interface SIM Parameters (Cont’d)

SIM Parameter Type Values Description

1 2 ... 89 90 91 92 93 94 95 96 97 98 99 ... 117 118

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