RAM 7.0 Guia do Utilizador descarregar pdf (Página 42)

LogiCORE IP Block Memory Generator v6.1

42 www.xilinx.com DS512 March 1, 2011

Product Specification

• Reset Type: This option determines if the reset is synchronous or asynchronous in Spartan-6

devices.

In addition to the above options, the options of output registers also affects reset functionality, since the

option to reset the memory latch depends on these options. Table 8 lists the dependency of the reset

behavior for Kintex-7, Virtex-7, Virtex-6, and Spartan-6 devices on these parameters. In these

configurations, the core output register does not exist. The reset behavior detailed in Table 8 uses Port

A as an example. The reset behavior for Port B is identical.

Table 8: Control of Reset Behavior in Kintex-7, Virtex-7, Virtex-6, and Spartan-6 for Single Port

Use RSTA Pin

Memory Primitives

Reset Memory Latch

Reset Priority for Port A

Reset Type (Spartan-6 Only)

S6 RESET BEHAVIOR V6 RESET BEHAVIOR

0 X X X X No control over reset No control over reset

(cannot

selected)

“CE”,

“SR”

“SYNC”,

“ASYNC”

Since no primitive output register

exists, the reset applies only to

the latch.

Reset occurs synchronously or

asynchronously depending on

the Reset Type option, and is

dependent or independent of the

input enable signal based upon

the Reset Priority. The reset

value is asserted for only one

clock cycle (only if input RST

signal is high for only one clock

and EN is high continuously).

Since no primitive output register

exists, the reset applies only to

the latch.

For Kintex-7, Virtex-7, and

Virtex-6, the priority of SR

cannot be set for the latch.

Therefore, reset occurs

synchronously when the enable

input is ‘1’. The reset value is

asserted for only one clock cycle

(only if input RST signal is high

for only one clock and EN is high

continuously).

11 0 “CE”

“SYNC”,

“ASYNC”

Fabric register used. Reset

occurs synchronously or

asynchronously depending on

the Reset Type option, and is

dependent or independent of the

input enable signal based on the

Reset Priority. Reset value

asserted for one clock cycle

(only if input RST signal is high

for only one clock and REGCE is

high continuously).

For Kintex-7, Virtex-7, and

Virtex-6 devices, the priority

cannot be set for the latch.

Therefore reset priority of "SR" is

not supported.Reset occurs

synchronously, and is

dependent or independent of the

input enable signal. Reset value

asserted for one clock cycle

(only if input RST signal is high

for only one clock and REGCE is

high continuously).

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