RAM 7.0 Guia do Utilizador descarregar pdf (Página 38)

LogiCORE IP Block Memory Generator v6.1

38 www.xilinx.com DS512 March 1, 2011

Product Specification

Figure 38 depicts how REGCE can be used to latch the data output to allow only intended data through.

Assume that only the memory primitive registers are used for port A, and that

EN is always asserted

and

RST is always deasserted. The data on the block RAM memory latch is labeled latch, while the

output of the last register, the block RAM embedded register, is the core output,

DOUT.

Reset Priority

For Kintex-7, Virtex-7, Virtex-6, and Spartan-6 devices, the Block Memory Generator core provides the

option to choose the reset priority of the output stages of the Block Memory. In previous architectures

such as Spartan-3A DSP and Virtex-5 devices, EN had a fixed priority over SSR (Synchronous Set Reset)

for the memory latch, and REGCE (Register Clock Enable) had a fixed priority over SSR for embedded

registers.

In Spartan-6 devices, when a user chooses the Reset Priority as CE, then the enable signal (ENA or ENB)

has a priority over the reset signal (RSTA or RSTB) for the memory latch, and the CE signal (REGCEA or

REGCEB) has a priority over the reset signal for the output registers. When Reset Priority is chosen as

SR, then the reset signal has a priority over the enable signal and the CE signal, in the case of the latch

and output registers respectively.

In Kintex-7, Virtex-7, and Virtex-6 devices, reset priority can be set only for the output registers and not

for the memory latch. When CE is the selected priority, then CE (REGCEA or REGCEB) has a priority

over reset (RSTA or RSTB). When SR is the selected reset priority, then reset has a priority over CE.

Figure 39 illustrates the reset behavior when the Reset Priority option is set to CE. Here, the first reset

operation occurs successfully because EN is high, but the second reset operation does not cause any

change in output because EN is low.

X-Ref Target - Figure 38

Figure 38: Flow Control Using REGCE

X-Ref Target - Figure 39

Figure 39: Reset Behavior When Reset Priority is Set to CE

CLKA

ADDRA[7:0]

AA BB CC

REGCE

LATCH

data(AA) data(BB) data(CC)

DOUT

data(AA) data(BB)

data(DD)

data(CC) data(DD)

CLKA

aa bb cc dd ee

0000 MEM(aa) INIT_VAL MEM(cc)

ENA

RSTA

ADDRA

DOUTA[15:0]

Disabled ReadReset When

ENA=’1’

Read No Reset

When EN=’0’

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 117 118

Comentários a estes Manuais

Sem comentários

RAM 7.0 Guia do Utilizador Página 38

Comentários a estes Manuais

Manuais e produtos relacionados com Amplificadores áudio RAM 7.0