RAM 7.0 Guia do Utilizador descarregar pdf (Página 15)

DS512 March 1, 2011 www.xilinx.com 15

Product Specification

LogiCORE IP Block Memory Generator v6.1

AXI4 Narrow Transactions

A narrow burst is defined as a master bursting a data size smaller than the block RAM data width. If the

burst type (AWBURST) is set to INCR or WRAP, then the valid data on the block RAM interface to the

AXI bus will rotate for each data beat. The Write and Read FSM handles each data beat on the AXI as a

corresponding data beat to the block RAM, regardless of the smaller valid byte lanes. In this scenario,

the AXI WSTRB is translated to the block RAM Write enable signals. The block RAM address only

increments when the full address (data) width boundary is met with the narrow Write to block RAM.

Figure 15 illustrates an example of AXI narrow Write bursting with a 32-bit block RAM and the AXI

master request is a half-word burst of four data beats. AWSIZE is set to 001b.

X-Ref Target - Figure 15

Figure 15: AXI4 Narrow Write Burst Transactions

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