RAM 8.0 BUX II Series Guia do Utilizador descarregar pdf (Página 18)

18 www.xilinx.com 7 Series FPGAs Memory Resources

UG473 (v1.11) November 12, 2014

Chapter 1: Block RAM Resources

output pipeline register is not used. This mode is the most power efficient. This mode is

not available in the SDP mode because it is identical in behavior to WRITE_FIRST mode.

Conflict Avoidance

The 7 series FPGAs block RAM is a true dual-port RAM where both ports can access any

memory location at any time. When accessing the same memory location from both ports,

you must, however, observe certain restrictions. There are two fundamentally different

situations: The two ports either have a common clock (synchronous clocking), or the clock

frequency and phase is different for the two ports (asynchronous clocking).

Asynchronous Clocking

Asynchronous clocking is the more general case, where the active edges of both clocks do

not occur simultaneously:

• There are no timing restrictions when both ports perform a read operation.

• When one port performs a write operation, the other port must not read or write

access the same memory location. Therefore, the READ_FIRST mode should be

avoided in true asynchronous applications, because there is no guarantee that the old

data will be read (in both TDP and SDP modes). The WRITE_FIRST mode is the

recommended mode when asynchronous clocks might cause simultaneous

read/write operations on the same port address. The simulation model produces an

error if this condition is violated. If this restriction is ignored, a read or write operation

produces unpredictable results. There is, however, no risk of physical damage to the

device. If a read and write operation is performed, then the write stores valid data at

the write location.

Synchronous Clocking

Synchronous clocking is the special case, where the active edges of both port clocks occur

simultaneously:

• Synchronous clocking is defined as both clock input pins being driven by the same

clock.

• There are no timing restrictions when both ports perform a read operation.

X-Ref Target - Figure 1-4

Figure 1-4: NO_CHANGE Mode Waveforms

CLK

ADDR

Disable Read

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) MEM(dd)

ReadWrite

MEM(bb)=1111

Write

MEM(cc)=2222

UG473_c1_04_052610

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 85 86

Comentários a estes Manuais

Sem comentários

RAM 8.0 BUX II Series Guia do Utilizador Página 18

Comentários a estes Manuais

Manuais e produtos relacionados com Amplificadores áudio RAM 8.0 BUX II Series