RAM 8.0 BUX II Series Guia do Utilizador descarregar pdf (Página 36)

36 www.xilinx.com 7 Series FPGAs Memory Resources

UG473 (v1.11) November 12, 2014

Chapter 1: Block RAM Resources

RAMB18E1 and RAMB36E1 Port Mapping Design Rules

The 7 series FPGAs block RAM are configurable to various port widths and sizes.

Depending on the configuration, some data pins and address pins are not used. Table 1-9

through Table 1-12 show the pins used in various configurations. In addition to the

information in these tables, these rules are useful to determine the RAMB port connections:

• When using RAMB36E1, if the DI[A|B] pins are less than 32 bits wide, concatenate

(32 – DI_BIT_WIDTH) logic zeros to the front of DI[A|B].

• If the DIP[A|B] pins are less than 4 bits wide, concatenate (4 – DIP_BIT_WIDTH)

logic zeros to the front of DIP[A|B]. DIP[A|B] can be left unconnected when not in

use.

• DO[A|B] pins must be 32 bits wide. However, valid data are only found on pins

DO_BIT_WIDTH – 1 down to 0.

• DOP[A|B] pins must be 4 bits wide. However, valid data are only found on pins

DOP_BIT_WIDTH – 1 down to 0. DOP[A|B] can be left unconnected when not in use.

• ADDR[A|B] pins must be 16 bits wide. However, valid addresses for non-cascadable

block RAM are only found on pin 14 to (15 – address width). The remaining pins,

including pin 15, should be tied High. Address width is defined in Table 1-9, page 27.

Cascadable Block RAM

To use the cascadable block RAM feature:

• Two RAMB36E1 primitives must be instantiated.

• Set the RAM_EXTENSION_A and RAM_EXTENSION_B attribute for one RAMB36E1

to UPPER, and another to LOWER.

• Connect the upper RAMB36E1 CASCADEINA and CASCADEINB ports to the

CASCADEOUTA and CASCADEOUTB ports of the lower RAMB36E1. The

CASCADEOUT ports for the upper RAMB36E1 do not require a connection. Connect

the CASCADEIN ports for the lower RAMB36E1 to either logic High or Low.

• The data output ports of the lower RAMB36E1 are not used. These pins are

unconnected.

• If placing location constraints on the two RAMB36E1s, they must be adjacent. If no

location constraint is specified, the Xilinx ISE software automatically manages the

RAMB36E1 locations.

• The address pins ADDR[A|B] must be 16 bits wide. Both read and write ports must

be one bit wide.

• The optional output registers can be used by setting the DO_REG = 1 attribute.

Figure 1-7, page 21 shows the cascadable block RAM.

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RAM 8.0 BUX II Series Guia do Utilizador Página 36