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UG473 (v1.11) November 12, 2014

FIFO Attributes

Full Flag

The Full flag is synchronous with WRCLK, and is asserted when there are no more

available entries in the FIFO queue. When the FIFO is full, the write pointer is frozen. The

Full flag is deasserted three write clock cycles after a subsequent read operation.

Write Error Flag

After the Full flag is asserted, any further write attempts do not increment the write

address pointer but do trigger the Write Error flag. The Write Error flag is deasserted when

Write Enable or Full is deasserted Low. This signal is synchronous to WRCLK.

Almost Full Flag

The Almost Full flag is set when the FIFO has the number of available empty spaces

specified by the ALMOST_FULL_OFFSET value or fewer spaces. The Almost Full flag

warns you to stop writing. It deasserts when the number of empty spaces in the FIFO is

greater than the ALMOST_FULL_OFFSET value. Assertion and deassertion is

synchronous to WRCLK. Flag latency is described in Table 2-4.

FIFO Attributes

Table 2-5 lists the FIFO18 and FIFO36 attributes. The size of the dual-clock FIFO can be

configured by setting the DATA_WIDTH attribute. The FIFO VHDL and Verilog Templates

section has examples for setting the attributes.

Table 2-5: FIFO18E1 and FIFO36E1 Attributes

Attribute Name Type Values Default Notes

ALMOST_FULL_OFFSET 13-bit

HEX

See Table 2-8 Setting determines the difference

between FULL and ALMOSTFULL

conditions. Must be set using

hexadecimal notation.

ALMOST_EMPTY_OFFSET 13-bit

HEX

See Table 2-8 Setting determines the difference

between EMPTY and ALMOSTEMPTY

conditions. Must be set using

hexadecimal notation.

FIRST_WORD_FALL_THROUGH Boolean FALSE,

TRUE

FALSE If TRUE, the first word written into the

empty FIFO appears at the FIFO output

without RDEN asserted.

DO_REG 1-bit

Binary

0, 1 1 For dual-clock (asynchronous) FIFO,

must be set to 1.

For synchronous FIFO, DO_REG must be

set to 0 for flags and data to follow a

standard synchronous FIFO operation.

When DO_REG is set to 1, effectively a

pipeline register is added to the output of

the synchronous FIFO. Data then has a

one clock cycle latency. However, the

clock-to-out timing is improved.

DATA_WIDTH Integer 4, 9, 18, 36, 72 4 Specifies the data width for the FIFO.

1 2 ... 48 49 50 51 52 53 54 55 56 57 58 ... 85 86

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