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7 Series FPGAs Memory Resources www.xilinx.com 83

UG473 (v1.11) November 12, 2014

ECC Timing Characteristics

Encode-Only ECC Write Timing

Refer to Figure 3-4.

• Setup/hold time for WREN and WRADDR are the same as standard ECC.

• At time TRDCK_DI_ECC (encode-only ECC), before time T1W, write data A (hex)

becomes valid at the DI[63:0] inputs of the block RAM.

• At time TRCKO_ECC_PARITY (encode-only ECC), after time T1W, ECC parity data

PA (hex) becomes valid at the ECCPARITY[7:0] output pins of the block RAM.

Encode-Only ECC Read Timing

• Encode-only ECC read timing are the same as normal block RAM read timing.

Decode-Only ECC Write Timing

• Decode-only ECC write timing is the same as normal block RAM write timing.

Decode-Only ECC Read Timing

• Decode-only ECC read timing is the same as standard ECC read timing.

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