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7 Series FPGAs Memory Resources www.xilinx.com UG473 (v1.11) November 12, 2014

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Revision History

The following table shows the revision history for this document.

Date Version Revision

03/01/2011 1.0 Initial Xilinx release.

03/28/2011 1.1 Updated disclaimer and copyright on page 2.

Updated values in Table 2-1, descriptions in Table 2-3, and values in Table 2-4. Modified

discussions in Almost Empty Flag, Full Flag, and Almost Full Flag sections. Updated

values in Table 2-7 and Table 2-8. Revised Figure 2-6. Revised discussion of clock event

2 and clock event 4 on page 59. Updated Case 3: Reading from a Full FIFO including

Figure 2-8.

04/14/2011 1.2 Added 7 Series FPGAs Block RAM and FIFO Differences from Previous FPGA

Generations. Added Table 1-2: Block RAM Resources in 7 Series Devices. Clarified valid

values for Read Width - READ_WIDTH_[A|B] and Write Width -

WRITE_WIDTH_[A|B] Updated the example in Block RAM Location Constraints.

Updated parameter names in Table 1-18.

Clarified the flag behavior in the Synchronous FIFO introduction. Revised the FIFO

Almost Full/Empty Flag Offset Range section including adding Note 1 to Table 2-8,

removing Equation 2-1 and revising Equation 2-2 to be the new Equation 2-1.

Updated port connection instructions for WEBWE[7:0].

10/18/2011 1.3 Added Stacked Silicon Interconnect. Added Artix-7 and Virtex-7 families to Table 1-2

and updated table notes.

11/18/2011 1.4 Updated second bullet in Changes from Virtex-6 FPGAs.

1 2 3 4 5 6 7 ... 85 86

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